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BL5373 data sheet 1 BL5373 low power real-time clock (rtc) shanghai belling general description the BL5373 is a cmos type real-time clock, which is connected to the cpu via two wires and capable of serial transmission of clock to the cpu. the BL5373 can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by two incorporated systems. since an oscillation circuit is driven at a constant voltage, it undergoes fluctuations of few voltage and consequently offers low current consumption (typ. 400na @ 5v) it also provides an oscillator halt sensing function applicable for data validation at power-on and other occasions. the product also incorporates a time trimming circuit that adjusts the clock with higher precision by adjusting any errors in crystal oscillator frequencies based on signals from the cpu. the crystal oscillator may be selected from 32khz or 32.768khz types. it adopts 8-pin sop or tssop package. features lowest supply current: 400na typ. @ 5v connected to the cpu via only 2-wires (max. 100khz) a clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, days, and days of the week) in bcd codes two systems output providing interrupt to the cpu output (period of one month to one second, interrupt halt function) two systems output of alarm functions oscillation halt sensing to judge internal data validity clock output of 32.768khz (32khz) (output controllable via a register) second digit adjustment by 30 seconds automatic leap year recognition up to the year 2099 12-hour or 24-hour time display selectable high precision time trimming circuit oscillator of 32.768khz or 32khz may be used cmos logic package: 8pin sop or tssop
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 2 ordering information package type number name description BL5373 sop8 plastic small outline package;8 pins; b ody width 3.9mm BL5373t tssop8 plastic thin shrink small outline package; 8 pins; body width 4.3mm block diagram pin configuration 8pin sop 8pin tssop pin definition pin no. symbol definition value in/out 1 intrb interrupt output b 0~12v out 2 scl serial clock line 0~5.5v in 3 sda serial data line 0~5.5v in/out 4 gnd ground power 0v power 5 intra interrupt output a 0~12v out 6 oscout oscillator circuit output 0~1.5v out 7 oscin oscillator circuit input 0~1.5v in 8 vdd supply voltage 1.8v~5.5v power
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 3 vdd and gnd b l 5 3 7 3 v d d g n d v d d g n d c 1 0 . 1 u + c 2 bypass capacitance the vdd pin is connected to the positive power supp ly and gnd to the ground. to prevent the possibility of no ise, when rapidly changing signal took place on BL5373 pin, w e have to place a capacitance beside the BL5373. one possibil ity is to place a bypass capacitance as close as to the bl537 3. the capacitance capacity of c2 could be determined per users demand, which provides large current passing abilit y between the pin and the ground. oscin and oscout these pins configure an oscillator circuit by conne cting a crystal oscillator between the oscin-oscout pins. the diagr am beside shows the connection method of such crystal oscilla tor circuit. its recommended to choose the right crystal oscillator parameter referring to the suppliers suggestion, since it do es determine the start-up reliability and oscillation stability prov ided by external devices. the influence of the distributing capacita nce should be considered when choosing capacitance capacity in an oscillator circuit. to minimize output distortion, both crysta l oscillator and capacitance should be installed as close to BL5373 pin as possible. crystal oscillator connection with external capacitance scl and sda scl and sda are serial clock line and serial data l ine, relatively. scl is used to input shift clock pulses to synchronize data input/output to and from the sda pin with this clock. sda inputs and outputs written or read data in synchronization wit h shift clock pulses from the scl pin. depend on different level of current, separate pull-up resist ance can be added to scl and sda on exterior circui t board. intra and intrb intra and intrb are two interrupt output ports and are both open drain outputs. when using BL5373 a pull-up resistance must be connected with pins of intra and intrb. intra could output periodic interrupt pulses and alarm interrup t (alarm-a, alarm-b); intrb could output 32.768khz clock pulses (when 32.768khz crystal is u sed), periodic interrupt pulses, alarm interrupt (alarm-b). when power is activated from 0v, it coul d output 32.768khz clock pulses (when 32.768khz crystal is used).
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 4 functional descriptions allocation of internal addresses internal address contents function 0h second counter counting and storing seconds in b cd codes 1h minute counter counting and storing minutes in b cd codes 2h hour counter counting and storing hours in bcd c odes 3h day of the week counter counting and storing days of the week in bcd codes 4h day counter counting and storing days in bcd cod es 5h month counter counting and storing months in bcd codes 6h year counter counting and storing years in bcd c odes 7h time trimming register storing adjusting parameter and external select con trol of crystal oscillator 8h alarm_a (minute register) storing minutes in timer a 9h alarm_a (hour register) storing hours in timer a ah alarm_a (day of the week register) storing days of the week in timer a bh alarm_b (minute register) storing minutes in timer b ch alarm_b (hour register) storing hours in timer b dh alarm_b (day of the week register) storing days of the week in timer b eh control register 1 storing ring enable, interrup t output port select, and periodic interrupt cycle select information fh control register 2 storing time display select, interrupt and alarm signal, oscillator halt sensing information calendar counter the BL5373 can exchange from year to second (lower two bits) with cpu. when the lower two bits of the year could be divided by 4, that year is leap year. it could automatically recognize the year between 2000 and 2099 and these data are stored separately in registers from 0h to 6h. control unit the control unit is a substantial part of the BL5373, under which all functionalities of the whole circuit is realized. the time display select, interrupt / alarm select and signal, output port select, as well as oscillation halt sensing information are all sent out by the control circuit. high precision time trimming function the BL5373 has an internal oscillation circuit capacitance cgnd and cvdd so that an oscillation circuit may be configured simply by externally connecting a crystal. the BL5373 incorporates a time trimming circuit (at internal address 7h) that adjusts gain or loss of the clock from the cpu up to approx. 189ppm( 194ppm when 32.000khz crystal is used) by approximately 3ppm steps to correct discrepancy in oscillation frequency. clock display is possible at much higher precision than conventional real-time clock while using a crystal with broader fluctuation in precision. even seasonal frequency fluctuation may be corrected by adjusting seasonal clock error. for those systems that have temperature detection precision of clock, function may be increased by correcting clock error according to temperature fluctuations. alarm function and periodic interrupt alarm function: the BL5373 has an alarm function that outputs an interrupt signal from ` intra or ` intrb output pins to the cpu when the day of the week, hour or minute corresponds to the setting. these two systems of alarms (alarm-a, alarm-b), each may output interrupt signal separately at a specific time. the
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 5 alarm may be selectable between on and off for each day of the week, thus allowing outputting alarm everyday or on a specific day of the week. the alarm-a is output from the ` intra pin while the alarm-b is output from either the ` intra or the ` intrb pins. polling is possible separately for each alarm function. periodic interrupt: the BL5373 can output periodic interrupt pulses in addition to alarm function from the ` intra and ` intrb pins. this frequency may be selected from 2hz, 1hz, 1/60hz, 1/3600hz and monthly by controlling register (at lower 3 bits of internal address eh) output selectively. output waveform for periodic interrupt may be selected from regular pulse waveform (2hz and 1hz) and waveforms (every second, every minute, every hour and every month) that are appropriate for cpu level interrupt. oscillation halt sensing the oscillation halt sending function uses a register (xstp bit at internal address fh) to store oscillation halt information. this function may be used to determine if the bl 5372 supply power has been booted from 0v and if it has been backed up. this function is useful for determining if clock data is valid or invalid. clock output the BL5373 may output oscillation frequency from intrb pin. this clock output is set for output by default, which is set to on or off by setting the register (internal address fh bit clen). it can also choose different crystal oscillator (32.768khz or 32.000khz) by setting the register (internal address 7h at bit xsl), and output clock pulses with two different frequencies.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 6 registers 1. clock counter at internal address 0-2h time digit display (in bcd code) second digits: range from 00 to 59 and carried to m inute digits when incremented from 59 to 00. minute digits: range from 00 to 59 and carried to h our digits when incremented from 59 to 00. hour digits: see descriptions on the ` 12/24 bit (section 7). carried to day and day-of-th e week digits when incremented from 11 p.m. to 12 a.m . or 23 to 00. any registered imaginary time should be replaced wi th correct time as carrying to such registered imaginary time digits from lower-order ones cause t he clock counter malfunction. second digit register (at internal address 0h) d7 d6 d5 d4 d3 d2 d1 d0 operation - s40 s20 s10 s8 s4 s2 s1 write 0 s40 s20 s10 s8 s4 s2 s1 read 0 undefined undefined undefined undefined undefined undefined undefined default minute digit register (at internal address 1h) d7 d6 d5 d4 d3 d2 d1 d0 operation - m40 m20 m10 m8 m4 m2 m1 write 0 m40 m20 m10 m8 m4 m2 m1 read 0 undefined undefined undefined undefined undefined undefined undefined default hour digit register (at internal address 2h) d7 d6 d5 d4 d3 d2 d1 d0 operation - - h20 or p/ ` a h10 h8 h4 h2 h1 write 0 0 h20 or p/ ` a h10 h8 h4 h2 h1 read 0 0 undefined undefined undefined undefined undefined undefined default *default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. 2. day-of-the-week counter (at internal address 3h) day-of-the-week digits are incremented by 1 when ca rried to 1-day digits. day-of-the-week digits display (incremented in sept imal notation): (w4,w2,w1) = (0,0,0) (0,0,1) (1,1,0) (0,0,0) the relation between days of the week and day-of-th e-week digits is defined as: sunday=(0,0,0); monday=(0,0,1); ; saturday=(1,1,0). (w4, w2, w1) should not be set to (1,1,1). d7 d6 d5 d4 d3 d2 d1 d0 operation - - - - - w4 w2 w1 write 0 0 0 0 0 w4 w2 w1 read 0 0 0 0 0 undefined undefined undefined default *the default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. 3. calendar counter (at internal address 4-6h) the automatic calendar function provides the follow ing calendar digit displays in bcd code and could recognize the leap year. day digits: range from 1 to 31 (for january, march , may, july, august, october, and december).
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 7 range from 1 to 30 (for april, june, september, an d november). range from 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary year s). month digits: range from 1 to 12 and carried to y ear digits when cycled to 1. carried to year digits when cycled from 12 to 1. year digits: range from 00 to 99 and 00,04,08, , 92, and 96 are counted as leap years. any registered imaginary time should be replaced wi th correct time as carrying to such registered imaginary time digits from lower-order ones cause t he clock counter malfunction. day digit register (at internal address 4h) d7 d6 d5 d4 d3 d2 d1 d0 operation - - d20 d10 d8 d4 d2 d1 write 0 0 d20 d10 d8 d4 d2 d1 read 0 0 undefined undefined undefined undefined undefined undefined default *default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. month digit register (at internal address 5h) d7 d6 d5 d4 d3 d2 d1 d0 operation - - - mo10 mo8 mo4 mo2 mo1 write 0 0 0 mo10 mo8 mo4 mo4 mo1 read 0 0 0 undefined undefined undefined undefined undefined default *default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. year digit register (at internal address 6h) d7 d6 d5 d4 d3 d2 d1 d0 operation y80 y40 y20 y10 y8 y4 y2 y1 write y80 y40 y20 y10 y8 y4 y2 y1 read undefined undefined undefined undefined undefined undefined undefined undefined default *default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. 4. time trimming register (at internal address 7h) d7 d6 d5 d4 d3 d2 d1 d0 operation xsl_ f6 f5 f4 f3 f2 f1 f0 write xsl_ f6 f5 f4 f3 f2 f1 f0 read 0 0 0 0 0 0 0 0 default *default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. xsl bit the ` xsl bit is used to select a crystal oscillator. set the ` xsl to 0 (default) to use 32.768khz set ` xsl to 1 to use 32khz. f6 to f0 the time trimming circuit adjust one second count based on this register readings when second digit is 00 20 or 40 seconds. normally, counting up to seconds is made once per 32,768 of clock pulse (or 32,000 when 32.000khz crystal is used) generated by the oscillator. setting data to this register activates the time trimming circuit. register counts will be incremented as ((f5, f4, f3, f2, f1, f0)-1) x2 when f6 is set to 0. register counts will be decremented as (( ` f5,
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 8 ` f4, ` f3, ` f2, ` f1, ` f0)+1) x2 when f6 is set to 1. counts will not change when (f6, f5, f4, f3, f2, f1, f0) are set to (*, 0, 0, 0, 0, 0, *). for example, when 32.768khz crystal is used. when (f6, f5, f4, f3, f2, f1, f0) are set to (0,1, 0, 1, 0, 0,1), counts will change as: 32768+ 29-1 *2=32824 (clock will be delayed) when second digit is 00, 20, or 40. when (f6, f5, f4, f3, f2, f1, f0) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain 32,768 without changing when second digit is 00, 20, or 40. when (f6, f5, f4, f3, f2, f1, f0) are set to (1,1,0,1,0,0,1), counts will change as: 32768+ -17+1 *2=32736 (clock will be advanced) when second digit is 00, 20, or 40. adding 2 clock pulses every 20 seconds: 2/ 32768*20 =3.051ppm (or 3.125ppm when 32.000khzcrystal is used), delays the clock by approx. 3ppm. likewise, decrementing 2 clock pulses advances the clock by 3ppm. thus the clock may be adjusted to the precision of 1.5ppm. note that the time trimming function only adjusts clock timing and oscillation frequency but 32.768khz clock output is not adjusted. 5. alarm register (alarm-a: internal address 8-ah; alarm-b: internal address b-dh) alarm-a minute register (at internal address 8h) d7 d6 d5 d4 d3 d2 d1 d0 operation - am40 am20 am10 am8 am4 am2 am1 write 0 am40 am20 am10 am8 am4 am2 am1 read 0 undefined undefined undefined undefined undefined undefined undefined default alarm-b minute register (at internal address bh) d7 d6 d5 d4 d3 d2 d1 d0 operation - bm40 bm20 bm10 bm8 bm4 bm2 bm1 write 0 bm40 bm10 bm10 bm8 bm4 bm2 bm1 read 0 undefined undefined undefined undefined undefined undefined undefined default alarm-a hour register (at internal address 9h) d7 d6 d5 d4 d3 d2 d1 d0 operation - - ah20,ap/ ` a ah10 ah8 ah4 ah2 ah1 write 0 - ah20,ap/ ` a ah10 ah8 ah4 ah2 ah1 read 0 0 undefined undefined undefined undefined undefined undefined default alarm-b hour register (at internal address ch) d7 d6 d5 d4 d3 d2 d1 d0 operation - - bh20,bp/ ` a bh10 bh8 bh4 bh2 bh1 write 0 0 bh20,bp/ ` a bh10 bh8 bh4 bh2 bh1 read 0 0 undefined undefined undefined undefined undefined undefined default alarm-a day-of-the-week register (at internal addre ss ah) d7 d6 d5 d4 d3 d2 d1 d0 operation - aw6 aw5 aw4 aw3 aw2 aw1 aw0 write 0 aw6 aw5 aw4 aw3 aw2 aw1 aw0 read 0 undefined undefined undefined undefined undefined undefined undefined default
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 9 alarm-b day-of-the-week register (at internal addre ss dh) d7 d6 d5 d4 d3 d2 d1 d0 operation - bw6 bw5 bw4 bw3 bw2 bw1 bw0 write 0 bw6 bw5 bw4 bw3 bw2 bw1 bw0 read 0 undefined undefined undefined undefined undefined undefined undefined default *default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. alarm-a, alarm-b hour register d5 is set to 0 for am and 1 for pm in the 12-hour display system. the register d5 indicates 1 0 digit of hour digit in 24-hour display system. to activate alarm operation, any imaginary alarm ti me setting should not be left to avoid un-matching. in hour digit display midnight is et to 12, noon is set to 32 in 12-hour display system. aw0 to aw6 (bw0 to bw6) correspond to the day-of-th e-week counter being set at (0, 0, 0) to (1, 1, 0). no alarm pulses are output when all of aw0 to aw6 ( bw0 to bw6) are set to 0. example of alarm time settings day-of-the-week 12-hour system 24-hour system alarm time settings sun mon tue wed thu fri sat 10h 1h 10m 1m 10h 1h 10m 1m 00:00am every day 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 05:27am every day 1 1 1 1 1 1 1 0 5 2 7 0 5 2 7 11:59am every day 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00pm on mon thru fri 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 05:56pm on wed 0 0 0 1 0 0 0 2 5 5 6 1 7 5 6 11:59pm on tue, thu, and sat 0 0 1 0 1 0 1 3 1 5 9 2 3 5 9 6. control register 1 (at internal address eh) d7 d6 d5 d4 d3 d2 d1 d0 operation aale bale sl2 sl1 test ct2 ct1 ct0 write aale bale sl2 sl1 test ct2 ct1 ct0 read 0 0 0 0 0 0 0 0 default *the default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 10 aale bale alarm-a alarm-b enable bits aale bale description operation 0 alarm-a alarm-b correspondence action invalid default 1 alarm-a alarm-b correspondence action valid sl2 sl1 interrupt output select bits sl2 sl1 description operation 0 0 outputs alarm-a, alarm-b, int to the intra. out puts 32k clock pulses to the intrb. default 0 1 outputs alarm-a, int to the intra. outputs 32k clock pulses, alarm-b to the intrb. 1 0 outputs alarm-a, alarm-b to the intra. outputs 32k clock pulses, int to the intrb. 1 1 outputs alarm-a to the intra. outputs 32k clock pulses, alarm-b, int to the intrb. by setting sl1 and sl2 bits, two alarm pulses (alar m-a, alarm-b), periodic interrupt output (int), 32k clock pulses may be output to the intra or intrb pins selectively. test BL5373 test bit test description operation 0 ordinary operation mode default 1 test mode the test bit is used for BL5373 test. set the test bit to 0 in ordinary operation. ct2 ct1 ct0 periodic interrupt cycle select bit description ct2 ct1 ct0 wave form mode cycle and intra intrb falling timing 0 0 0 - intra intrb at high level 0 0 1 - intra intrb at low level 0 1 0 pulse mode 2hz duty 50% 0 1 1 pulse mode 1hz duty 50% 1 0 0 level mode every second synchronized with second count up 1 0 1 level mode every minute 00 second of every minute 1 1 0 level mode every hour 00 minute 00 second of every hour 1 1 1 level mode every month the 1 st day 00 a.m. 00 minute 00 second of every month 1 pulse mode: outputs 2hz, 1hz clock pulses. for rel ationships with counting up of seconds see the diagram below. in the 2hz clock pulse mode, 0.496s clock pulses an d 0.504s clock pulses are output alternatively. duty cycle for 1hz clock pulses becomes 50.4%. 2 level mode: one second, one minute or one month may be selected for an interrupt cycle. counting up of seconds is matched with falling edge of interrupt output.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 11 3 when the time trimming circuit is used, periodic in terrupt cycle changes every 20 seconds. pulse mode: l duration of output pulses may chang e in the maximum range of 3.784ms ( 3.875ms when 32khz crystal is used). for example, duty will be 50 0.3784% (or 50 0.3875% when 32khz crystal is used) at 1hz. level mode: frequency is one second may change in t he maximum range of 3.784ms ( 3.875ms when 32khz crystal is used). relation between mode waveforms and crfg bit pulse mode level mode ctfg intra(intrb) ctfg=0 ctfg=0 second count-up second count-up second count-up 7. control register 2 (at internal address fh) d7 d6 d5 d4 d3 d2 d1 d0 operation - - 12_/24 adj clen_ ctfg aafg bafg write 0 0 12_/24 xstp clen_ ctfg aafg bafg read 0 0 undefined 1 0 0 0 0 default *the default means read value when xstp bit is set to 1 by starting up from 0v, or supply voltage drop, etc. ` `` ` 12/24 ` 12/24-hour time display system selection bit ` 12/24 description 0 12-hour time display system 1 24-hour time display system being set this bit at 0 indicates 12-hour display system while 1 indicates 24-hour system.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 12 time display digit table 24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system 00 12(am12) 12 32(pm12) 01 01(am1) 13 21(pm1) 02 02(am2) 14 22(pm2) 03 03(am3) 15 23(pm3) 04 04(am4) 16 24(pm4) 05 05(am5) 17 25(pm5) 06 06(am6) 18 26(pm6) 07 07(am7) 19 27(pm7) 08 08(am8) 20 28(pm8) 09 09(am9) 21 29(pm9) 10 10(am10) 22 30(pm10) 11 11(am11) 23 31(pm11) either the 12-hour or 24-hour time display system s hould be selected before writing time data. adj 30 second adjust bit adj description 0 ordinary operation 1 second digit adjustment the following operations are performed by setting t he second adj bit to 1 1 for second digits ranging from 00 to 29 seconds time counters smaller than seconds are reset and second digits are set to 00 . 2 for second digits ranging from 30 to 59 seconds : time counters smaller than seconds are reset and second digits are set to 00 . minute digits are incremented by 1. second digits are adjusted within 122us(within 125u s: when 32khz crystal is used) from writing operation to adj. the adj bit is for write only and allows no read op eration. xstp oscillator halt sending bit xstp description operation 0 ordinary oscillation 1 oscillator halt sensing default the xstp bit senses the oscillator halt. when oscillation is halted after initial power on f rom 0v or drop in supply voltage the bit is set to 1 and which remains to be 1 after it is restarted. this bit may be used to judge validity of clock and calendar count data after pow er on or supply voltage drop. when this bit is set to 1, ` xsl f6 to f0 ct2 ct1 ct0 aale bale sl2 sl1 ` clen and test bits are reset to 0. ` intra will stop output and the ` intrb will output 32khz clock pulses. the xstp bit is set to 0 by setting the control r egister 2 (address fh) during ordinary oscillation.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 13 clen 32khz clock output bit ` clen description operation 0 32khz clock output enabled default 1 32khz clock output disabled by setting this bit to 0, output of clock pulses of the same frequency as the crystal oscillator is enabled. ctfg periodic interrupt flag bit ctfg description operation 0 periodic interrupt output=off default 1 periodic interrupt output=on this bit is set to 1 when periodic interrupt puls es are output ( ` intra or ` intrb= l). the ctfg bit may be set only to 0 in the interrup t level mode. setting this bit to 0 sets either the ` intra or the ` intrb to off (h). when this bit is set to 1 no thing happens. aafg bafg alarm-a, alarm-b flag bit alarm-a alarm-b description operation 0 unmatched alarm register with clock counter defau lt 1 matched alarm register with clock counter the alarm interruption is enabled only when the aal e, bale bits are set to 1. this bit turns to 1 when matched time is sensed for each a larm. the aafg, bafg bit may be set only to 0. setting this bit to 0 sets either the ` intra or the ` intrb to the off h. when this bit is set to 1 nothing happens. when the aale, bale bit is set to 0, alarm operat ion is disabled and 0 is read from the aafg, bafg bit. output relationships between aafg bafg bit and ` intra ` intrb aafg(bafg) intra(intrb) time matche time matched time matched aafg(bafg)=0 aafg(bafg)=0
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 14 transmission system of interface communication protocol determines: circuits in the equipment which sends data through sda bus are regarded as emitters, contrarily, circuits in the e quipment which receives data through sda bus are regarded as receivers. master equipment and master circuit control data transmission; slave circuit is controlled. typical system bus structure slave receiver slave emitter / receiver slave receiver master emitter/receiver master emitter/receiver vdd sda scl data validity protocol data transmission protocol determines: transmit one bit data in every clock cycle. sda must be kept at a certain state while scl is at the h state as shown below during data transmission. start and stop conditions the scl and sda pins are at the h level when no d ata transmission is made. changing the sda from h to l when the scl and the sda are h ac tivates the start condition and access is started. changing the sda from l to h when the scl is h activates stop condition and accessing stopped. start and stop conditions as the arrival of the start condition, master emitt er must send out an address command bit, which includes slave address and r/w model; when a certain receiver in bus is chosen, it will send ack signal and sda changes into low volta ge. ack signal indicates the success of data transmission. when scl clock drops, emitter se nds continuously 8 bits and releases the data bus (sda changes into high voltage).
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 15 the slave address the high effective 7 bits (bit7---bit1) in the addr ess byte are defined as device type id. in BL5373, these 7 bits are 0110010. the lowest bit0 i s defined as r/w model. when this bit is 1, it is read model, while 0 is write model. the slave address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 1 1 0 0 1 0 r/w bit7bit1 the slave address of the BL5373 is defined as 01100 10 bit0 r/w definition 1 is read model 0 is write model data transmission format in the interface communica tion interface generates no chip enable signals. in pla ce of it each device has a 7bit slave address allocated. the first 1byte is allocated to this 7bi t of slave address and to the command (r/ ` w) for which data transmission direction is designated b t he data transmission thereafter. the slave address of the BL5373 is specified at (01 10010). at the end of data transmission/receiving stop cond ition is generated to complete transmission. however, if start condition is generated without ge nerating stop condition, repeated start condition i s met and transmission/receiving data may be continue d by setting the slave address again. use this procedures when the transmission direction needs t be changed during one transmission. data is written into the slave from the master when data is read from the slave immediately after 7bit addressing from the master
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 16 when the transmission direction is to be changed d uring transmission data transmission write format in the BL5373 a first send 7 address bit(0110010), the eighth bit is write command 0. b when the ninth bit is ack signal, BL5373 is under writing condition. c in the following byte, the high 4 bits are determi ned as internal address in BL5373(0h-fh), the low 4 bits are transmission mode l. d after another bits ack signal, it starts writing data normally. e after writing 1 byte data, there will be 1 bit ack signal and then writing data in next 1 byte starts. only when there is a stop signal in th e bit after ack signal, can the writing operation be stopped. example of data writing (when writing to internal a ddress 4h to 5h) data transmission read format in the BL5373 the BL5373 allows the following three readout metho ds of data from an internal register. the first method to reading data from the named int ernal address a)the first three steps are the same as write model b) after one bit ack signal, a new start signal wil l be produced to change the direction of data transmission in interface connection. c)then send 7 address bit(0110010), the eighth bit command is 1, BL5373 is under data reading condition.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 17 d) after another bits ack signal, it starts readin g data normally. e) when a byte data is read and cpu sends 1 bit ack signal, a next byte data can be read. only when the 1 bit ack signal which is sent by cpu is high voltage, can the reading operation be stopped and then cpu sends stop signal s. example 1 of data read (when data is read from 7h t o 9h) ) the second method to reading data from the intern al register is to start immediately after writing to the internal address pointer and the tra nsmission format register. set 4h to the transmission format register when this method is us ed. example 2 of data read (when data is read from inte rnal address dh to 0h).
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 18 ) the third method to reading data from the interna l register is to start reading immediately after writing to the slave address(0110010) and the ( r/ ` w) bit. since the internal address pointer is set to fh by default , this method is only effec tive when reading is started from the internal address fh. example 3 of data read (when data is read from inte rnal address fh to 3h). data transmission under special condition the BL5373 hold the clock tentatively for duration from start condition to stop condition to avoid invalid read or write clock on carrying clock. to p revent invalid read or write clock shall be made during one transmission operation. when 0.5 to 1.0 seconds elapses after start condition any access to the BL5373 is automatically released to release tentative hold of the clock and access from the cpu is forced to be terminated (automatic resume fu nction from the interface). also a second start condition after the first condi tion and before the stop condition is regarded as the repeated start condition. therefore, when 0.5 to 1.0 seconds passed after the first start condition, access to the BL5373 is automatically re leased. the user shall always be able to access the real-ti me clock as long as the following two conditions are met. 1 no stop condition shall be generated until clock re ad/write is started and completed. 2 one cycle read/write operation shall be completed w ithin 0.5 seconds. bad example of reading from seconds to hours (inval id read) (start condition) (read of seconds) (read of minutes) (stop condition) (start condition) (read of hour) (stop condition) assuming read was started at 09:59:59pm, and while reading seconds and minutes the time advanced to 10:00:00 pm. at this time second digit is hold s o the read as 59:59. BL5373 confirms (stop condition) and carry second digit being hold and th e time changes to 10:00:00 pm. then, when the hour digit is read, it changes to 10. the wrong res ults of 10:59:59 will be read.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 19 configuration of oscillating circuit and time trimm ing circuit a) in general crystal oscillators are classified by th eir central frequency of cl (load capacitance) and available further grouped in several ranks as 10 20 and 50ppm of fluctuations in precision. b) the fluctuation of ic circuit frequency is 5~10ppm at room temperature. c) here, the clock accuracy at room temperature var ies along with the variation of the characteristic of crystal oscillat or. configuration of oscillating circuit because the adjustment of crystal oscillator freque ncy is also the adjustment of clock frequency, so the former adjustment can be done thr ough c in & c out on the both sides of crystal. BL5373 clock cooperates with c in & c out , so oscillator frequency can be referred to crystal c l . general, relation between c l and c in or c out is as follows cs cout cin cout cin cl + + = * c s board floating capacitance if crystal oscillator frequency is on the higher si de, the cl should be decreased, contrarily, the cl should be increased. according to this standard, the best cl is chosen t o adjust frequency and clock frequency. for example: if the frequency is on the higher side, it can be lowed by attaching a c gout capacitor.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 20 time trimming circuit using the time trimming circuit gain or lose of clo ck may be adjusted with high precision by changing clock pulses for one second every 20 seconds. 1. when oscillation frequency *1 > target frequency *2 clock gain adjustment amount *3 = ) 20 * arg ( 2 * )1.0 arg ( y etfrequenc t nfrequency oscillatio y etfrequenc t frequency oscilation + - = (oscillation frequency C target frequency) x 10 +1 *1) oscillation frequency: clock frequency output fr om the ` intrb pin *2) target frequency: typ. 32.768khz to 32.000khz *3) adjustment amount: a value to be set finally to f6 to f0 bits. this value is expressed in 7 bit bi nary digits with sign bit (twos compliment). 2. when oscillation frequency = target frequency (no c lock gain or loss) set the adjustment value to 0 or +1, or C64, or C63 to disable adjustment. 3. when oscillation frequency < target frequency (clock los ses) adjustment amount = ) 20 * arg ( 2 * ) arg ( y etfrequenc t nfrequency oscillatio y etfrequenc t frequency oscilation - = (oscillation frequency C target frequency) x 10 example of calculations 1) when oscillation frequency = 32770khz; target fr equency = 32768khz adjustment value = 32770-32768+0.1 /(32770*2/(32768*20)) =(32770-32768)*10+1=21 set f6 f5 f4 f3 f2 f1 f0 = 0 0 1 0 1 0 1 2) when oscillation frequency =32762khz; target fre quency = 32768khz adjustment value = 32762-32768 /(32762*2/(32768*20)) = (32762-32768)*10=-60 to express C60 in 7bi binary digits with sign bit ( twos compliment) subtract 60(3ch) from 128(80h) in the above case, 80h-3ch=44h thus set f6 f5 f4 f3 f2 f1 f0 = 1 0 0 0 1 0 0 after adjustment, adjustment error against the targ et frequency will the approx. 1.5ppm at a room temperature. notice: 1) clock frequency output from the ` intrb pin will change after adjustment by the clock adjustment circuit.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 21 2) adjustment range: a)when oscillation frequency is higher than targe t frequency, the range of adjustment values is f6 f5 f4 f3 f2 f1 f0 = 0 0 0 0 0 0 1 to (0 1 1 1 1 1 1) and actual adjustable amount shall be -3.05ppm to C189. 2ppm (-3.125ppm to 193.7ppm for 32000hz crystal). b) when oscillation frequency is lower than targe t frequency, the range of adjustment values is f6 f5 f4 f3 f2 f1 f0 = 1 1 1 1 1 1 1 to 1 0 0 0 0 1 0 and actual adjustable amount shall be 3.05ppm to 18 9.2ppm (3.125ppm to 193.7ppm for 32000hz crystal) output waveforms the following three output waveforms can be output from the ` intra ( ` intrb) pin. 1 alarm interrupt when a registered time for alarm (such as day-of-t he-week, hour or minute) coincide with calendar counter (such as day-of-the-week, hour or minute) i nterrupt to the cpu are requested with the output pin being on l. alarm interrupt consists o f alarm_a and alarm_b, both have equivalent functions. 2 periodic interrupt outputs an output waveform selected by setting the periodic interrupt frequency select bit. waveforms include pulse mode and level mode. 3 32khz clock output clock pulses generated in the oscillation circuit are output as they are. control of the ` `` ` intra ( ` `` ` intrb) output (flag bit, enable bit, interrupt outp ut select bit) of the three output wave forms listed above, interr upt output conditions may be set by setting the fla g bit that monitors output state on the register, the enable bit that enables an output wave form and th e output select bit that selects either ` intra or ` intrb to be output. interrupt output select bit sl2 sl1 (d5 d4 at eh) flag bit enable bit 0 0 0 1 1 0 1 1 alarm_a aafg (d1 at fh) aale (d7 at eh) ` intra ` intra ` intra ` intra alarm_b bafg (d0 at fh) bale (d6 at eh) ` intra ` intrb ` intra ` intrb periodic interrupt ctfg (d2 at fh) disabled at ct2=ct1=ct0=0 (d2 to d0 at eh) ` intra ` intra ` intrb ` intrb 32khz clock output no ` clen (d3 at fh) ` intrb ` intrb ` intrb ` intrb when power on (xstp=1) since aale=bale=ct2=ct1=ct0= ` clen=sl2=sl1=0, ` intra=off (h) and 32khz clock pulses are output f rom the ` intrb pin.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 22 when more than one output waveforms are output from a single output pin, the output will have or wave form of negative logic of both. alarm-a alarm-b intra alarm interrupt for setting an alarm time, designated time such as day-of-the-week, hour or minute should be set to the alarm registers being aale bale bit to 0. after that set the aale bale bit to 1, from this moment onward when such registered alarm time coinc ide the value of calendar counter the ` intra ( ` intrb) comes down to l (on). the ` intra ( ` intrb) output can be controlled by operating to the aale (bale) and aafg (bafg) bits. periodic (clock) interrupt the ` intra ( ` intrb) pin output, the periodic interrupt cycle sel ect bits (ct2, ct1, ct0) and the interrupt output select bits (sl2, sl1) can be used to interrupt the cpu in a certain cycle. the periodic interrupt cycle select bits can be used to select either one of two interrupt output modes: t he pulse mode and the level mode.
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 23 description ct2 ct1 ct0 wave form mode cycle and intra(intrb) falling timin g 0 0 0 - intra intrb off (default) 0 0 1 - intra intrb fixed at l 0 1 0 pulse mode 2hz (duty 50%) 0 1 1 pulse mode 1hz (duty 50%) 1 0 0 level mode every second (coincident with seco nd count-up) 1 0 1 level mode every minute (00 second of every m inute) 1 1 0 level mode every hour (00minute 00second of e very hour) 1 1 1 level mode every month (1st day, 00:00:00 a.m .of every month) 1 pulse mode: output 2hz, 1hz clock pulses. for rela tionships with counting up of seconds see the diagram below. in the 2hz clock pulse mode, 0.496s clock pulses an d 0.504s clock pulse are output alternatively. duty cycle for 1hz clock pulses becomes 50.4%. 2 level mode: one second, one minute one month may be selected for an interrupt cycle. counting up of seconds is matched with falling edge of inter rupt output. 3 when the time trimming circuit is used, periodic in terrupt cycle changes every 20 seconds. pulse mode: l duration of output pulses may chan ge in the maximum range of 3.784ms ( 3.875ms when 32khz crystal is used) for example, duty will be 50 0.3784% (or 50 0.3875% when 32khz crystal is used) at 1hz. level mode: frequency in one second may change in the maximum range of 3.784ms ( 3.875ms when 32khz crystal is used). relation between mode waveforms and crfg bit pulse mode level mode
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 24 32khz clock output the crystal oscillator can generate clock pulses of 32khz from the ` intrb pin. the pin is changed to h by setting the ` clen bit to 1. 32khz clock pulse output will not be affected from settings in the clock adjustment register. when power on (xstp=1), 32khz clock pulses are output from the ` intrb pin. oscillator halt sensing oscillation halt can be sensed through monitoring the xstp bit with preceding setting of the xstp bit to 0 by writing data to the control register 2.upon oscillator halt sending, the xstp bit is switched from 0 to 1. this function can be applied to judge clock data validity. when the xstp bit is 1, ` xsl, f6 to f0, ct2, ct1, ct0, aale, bale, sl2, sl1, ` clen and test bits are reset to 0. *1 the xstp bit is set to 1 upon power-on from 0v. note that any instantaneous power disconnection may cause operation failure. *2 once oscillation halt has been sensed, the xstp bit is held at 1 even if oscillation is restarted. ensure error-free oscillation half sensing by preventing the following events: 1 instantaneous disconnection of vdd 2 condensation on the crystal oscillator 3 generation of noise on the pcb in the crystal oscillator 4 application of voltage exceeding prescribed maximum ratings to the individual pins of the ic
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 25 dc characteristics t opt =-40 to +85 , gnd=0v, vdd=3.6v, f osc =32,768hz or 32,000hz symbol item pin name conditions min. typ. max. unit vih h input voltage scl, sda 0.8vdd 6.0 v vil l input voltage scl, sda -0.3 0.3vdd v iol1 intra, intrb vol1=0.4v 1 ma iol2 l output current sda vol2=0.6v 6 ma iilk input leakage current scl vi=6vorgnd vdd=6v -1 1 ua operating voltage 1.8 5.5 v vdd counting voltage vdd gnd 1.2 5.5 v ioz output off state leakage current sda, intra, intrb vo=6vorgnd vdd=6v -1 1 ua idd standby current vdd vdd=5v, topt=25 scl,sda=5v 0.4 ua ac characteristics characteristics parameter t a = -40 to +85 v dd =4.5v to 5.5v symbol item conditions min. max. unit f scl scl clock frequency 0 100 khz t low scl clock l time 4.7 us t high scl clock h time 5 us t buf bus release time before next data is transmitted 4.7 us t su:sta start condition setup time 4.7 us t su:sto stop condition setup time 4.7 us t hd:sta start condition hold time 4 us t hd:sto stop condition hold time 4 us t su:dat data setup time 250 ns t hd:dat data input hold time 0 ns t hd data output hold time scl negedge to sda data changes 0 ns t aa clock output scl negedge to sda data availed 0.3 3.5 us t r rising time of scl and sda (input) 1 us t f falling time of scl and sda (input) 300 ns t i spike width that can be removed with input filter 100 ns
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 26 absolute maximum ratings symbol item conditions ratings unit vdd supply voltage -0.3 to +7.0 v vi input voltage scl sda -0.3 to +7.0 v vo1 output voltage 1 sda -0.3 to +7.0 v vo2 output voltage 2 intra, intrb -0.3 to +12.0 v topt operating temperature -40 to +85 tstg storage temperature -55 to +125
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 27 typical applications example of circuit (a) (b) 1. mount the high-and low-frequency by-pass capacitors c0 and c1 (typ. c1=10uf, c2=0.1uf) 2. the typical volume of pull-up resistance r0~r3 is 10k 3.batt and vccs voltage: v batt v vcc 4. connect the pull-up resistor of the intra pin or the intrb pin to two different positions depending battery back-up: a when the spare battery supplies power, intra (b) is not used. b when the spare battery supplies power, intra (b) is used. example of interface circuit to the cpu
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 28 package dimmensions sop8 mm inches symbol min typ. max min typ. max a 1.35 - 1.75 0.053 - 0.069 a1 0.10 - 0.25 0.004 - 0.010 b 0.33 - 0.51 0.013 - 0.020 c 0.19 - 0.25 0.007 - 0.010 d 4.80 - 5.00 0.189 - 0.197 ddd - - 0.10 - - 0.004 e 3.80 - 4.00 0.150 - 0.157 e - 1.27 - - 0.050 - h 5.80 - 6.20 0.228 - 0.244 h 0.25 - 0.50 0.010 - 0.020 l 0.40 - 0.90 0.016 - 0.035 0 o - 8 o 0 o - 8 o
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet 29 tssop8 dimensions(mm are the original dimensions) unit a max. a1 a2 a3 bp c d (1) e (2) e mm 1.10 0.15 0.05 0.95 0.80 0.25 0.32 0.12 0.25 0.10 3.10 2.90 4.60 4.20 0.65 unit h e l lp v w y z (1) mm 6.70 6.10 0.94 0.80 0.20 0.1 0.1 0.1 0.70 0.35 10 0 0 0 notes 1.plastic or metal protrusions of 0.15mm maximum pe r side are not included 2.plastic or metal protrusions of 0.25mm maximum pe r side are not included
shanghai belling shanghai belling shanghai belling shanghai belling BL5373 data sheet v1.0 30 revision summary the contents of this document are provided in conne ction with shanghai belling, inc. products. shangha i belling makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any t ime without notice. no license, whether express, implied, arisi ng by estoppel or otherwise, to any intellectual pr operty rights is granted by this publication. except as set forth in shanghai belling's standard terms and conditions o f sale, shanghai belling assumes no liability whatsoever, a nd disclaims any express or implied warranty, relat ing to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or infringement of any intellectual property right. shanghai belling's products are not designed, inten ded, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain l ife, or in any other application in which the failure of shanghai bellin g 's product could create a situation where persona l injury, death, or severe property or environmental damage may occur. shanghai belling reserves the right to discontinue or make changes to its products at any time without notice. ? 2010 shanghai belling, inc. all rights reserved.

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